为了避免由于数据在不同层的 cache 所带来的运行时间的差异，我想要关闭 CPU cache，让所有数据都存在 DRAM 里。稍微搜索了一下，好像没什么清晰的解决方案，想问问有没有大神知道如何做。
谢谢！
This topic created in 2154 days ago, the information mentioned may be changed or developed.
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byaiu Jul 19, 2020 via Android
上 8086,80286 这种 CPU，可完美解决
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mightofcode Jul 19, 2020
为什么会这这种需求
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redsonic Jul 19, 2020
intel:
;Step 1 - Enter no-fill mode mov eax, cr0 or eax, 1<<30 ; Set bit CD and eax, ~(1<<29) ; Clear bit NW mov cr0, eax ;Step 2 - Invalidate all the caches wbinvd ;All memory accesses happen from/to memory now, but UC memory ordering may not be enforced still. ;For Atom processors, we are done, UC semantic is automatically enforced. xor eax, eax xor edx, edx mov ecx, IA32_MTRR_DEF_TYPE ;MSR number is 2FFH wrmsr ;P4 only, remove this code from the L1I wbinvd AMD: ;Step 1 - Disable the caches mov eax, cr0 or eax, 1<<30 mov cr0, eax ;For some models we need to invalidated the L1I wbinvd ;Step 2 - Disable speculative accesses xor eax, eax xor edx, edx mov ecx, MTRRdefType ;MSR number is 2FFH wrmsr 善用搜索 how-can-the-l1-l2-l3-cpu-caches-be-turned-off-on-modern-x86-amd64-chips |
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vcfghtyjc OP |
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secondwtq Jul 20, 2020
@Gwzlchn 德国有人测过 x86： https://uops.info
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vicsun2020 Jul 20, 2020 via iPhone
@Nich0la5 估计是为了写论文。。
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